The present invention relates to output circuits for high speed digital integrated circuit devices. Those digital integrated circuit devices generate digital pulses with typical frequencies up to several MHz.
The sharp rising and falling edges of the digital pulses generated by those digital integrated circuit devices induce so called switching noise, e.g. harmonic distortion, crosstalk, voltage supply dips, peak currents, etc. On the one hand, this switching noise presents several disruptive effects on the internal operation of the circuit, such as pulsing of noise on input and internal circuit ground and power supply lines or local threshold shifts in the reference voltages for high and low potential data signals causing false data signals. On the other hand, the noise causes EMC (electromagnetic compatibility) problems, e.g. radio frequency radiation interference and electromagnetic induction interference noise which may interfere with a host system.
Now, EMC requirements for digital integrated circuit devices are determined on a European level and have to be respected by any device sold. In order to meet these EMC requirements, the interference of the digital circuit with its environment has to be reduced, which means that the steepness of the rising and falling edges of the outgoing signal has to be reduced.
A solution to the above-mentioned problem is disclosed in European patent application EP-A-0 443 435. It relates to an output buffer circuit for integrated digital devices comprising a driving device with an adjustable drive capability. The driving device includes a first and a second output driving stage of different drive capabilities. These two driving stages are connected in parallel and operated sequentially in order to limit the charging or discharging currents of the external load capacitance.
During a transition from low to high at the input of the output buffer, only a first driving stage with a small drive capability is operated in a first step, whereby the external load capacitance is charged by a small charging/discharging current generated by the first driving stage. During this first charging step, the output voltage of the buffer circuit is permanently sensed and when the output voltage exceeds a predetermined threshold value, the second driving stage with a large drive capability is activated. The charging current is then considerably raised during this second step, thereby rapidly completing the charging of the external load capacitance.
During a transition from high to low at the input, the driving stages are operated accordingly in two steps. In a first step the external load capacitance is discharged by a small discharging current generated in the first driving stage. After the output voltage has dropped below a certain threshold value, the drive capability of the driving device is adjusted by activating the second driving stage whereby the discharging of the external load is rapidly completed.
By adjusting the drive capability of the driving device each time that the output voltage of the buffer circuit passes over a predetermined threshold value and thereby charging or discharging the external load capacitance in two steps as described, the output buffer circuit of EP-A-0 443 435 achieves an overall reduction of the steepness of the output signal compared to a driving device with a fixed drive capability, e.g. a single driving stage.
One drawback of the output buffer circuit of EP-A-0 443 435 is, that the steepness of the output pulse is largely dependent on the external load capacitance. In fact, in the presence of a large load capacitance, the small charging/discharging current during the first step and the large charging/discharging current during the second step result in a slow rise/fall of the output voltage, whereas the same currents in the presence of a small load capacitance result in a much faster rise/fall of the output voltage.
In other words, the steepness of the output pulses of the output buffer circuit described in EP-A-0 443 435 is largely depends on the output capacity of the circuit which is driven by the digital integrated circuit.